Tiny Tapeout: put your design on a real chip, after learning the logic
Tiny Tapeout makes it quicker, easier and cheaper to get your own design manufactured on a real chip. Many designs share one chip on a shuttle: you submit a small digital design, drawn with logic gates in Wokwi or written in Verilog from its templates (some shuttles also take analog designs), and it is placed in a tile, about 160 by 100 micrometres on the shuttles TT04 to TT10, using the open-source SkyWater 130 nm process design kit. Pricing depends on the size of the design, the shuttle and whether it is analog or digital, and the FAQ warns that manufacturing takes 6 to 9 months. Its Digital Design Guide starts with logic gates, then puzzles such as a flip-flop, an edge detector and a full adder. Tiny Tapeout is how you get a design onto silicon; digiwleea is a free place to learn the logic that design is made of.
What Tiny Tapeout is good at
It turns chip making from an industry privilege into a class project: a real tapeout of your own design at a fraction of a full chip's cost, with templates, a design guide, workshops and a community to help, and universities among its customers. Seeing your own logic come back as a packaged chip is hard to beat as motivation. (digiwleea is an independent project, not affiliated with Tiny Tapeout.)
How digiwleea helps before you submit
A Tiny Tapeout design is digital logic: gates, flip-flops, counters and small state machines. digiwleea teaches exactly that, from the transistor up, in the browser: you build the gates from CMOS transistors, then a full adder, an edge detector, flip-flops, a 7-segment counter and a CPU, each checked against its truth table or its clocked behaviour, in a 40+ level course with an AI tutor (Wleea). It does not produce Tiny Tapeout submissions: design and submit in Wokwi or Verilog with Tiny Tapeout's templates, and use digiwleea to understand and test the logic first. The Verilog lessons are a bridge to the HDL route.
| Tiny Tapeout | digiwleea | |
|---|---|---|
| What you get | Your design manufactured on a shared chip | A working simulation of your circuit |
| Design entry | Wokwi gates or Verilog templates | Transistors, gates and parts in a browser lab |
| Process | Open-source SkyWater 130 nm PDK | Switch-level simulation, no silicon |
| Time | 6 to 9 months to manufacture | Instant, in the browser |
| Price | Depends on design size and shuttle | Free lab and Act I; Premium for the full course |
No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.
More comparisons: HDL, FPGA and chip design tools
See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.
Open the digiwleea lab →Frequently asked
What is Tiny Tapeout?
An educational project that makes it quick, easy and cheap to get a small digital or analog design manufactured on a real chip, by sharing one chip between many designs on a shuttle.
How long does Tiny Tapeout take?
Its FAQ says chips take between 6 and 9 months to manufacture, so expect up to a year's wait after a shuttle closes.
Do I need to know Verilog for Tiny Tapeout?
No. You can draw a design with logic gates in Wokwi using its templates, or write Verilog if you prefer an HDL.
Can digiwleea make a Tiny Tapeout design?
No. digiwleea simulates logic in the browser and does not export Tiny Tapeout submissions. It is a place to learn and test the gates, flip-flops and counters a design is built from.