Icarus Verilog vs Verilator vs GHDL: which free HDL simulator?
Icarus Verilog, Verilator and GHDL are the best-known free, open-source simulators for hardware description languages. Icarus Verilog (GPL-2.0) aims to compile all of Verilog as defined by IEEE 1364, plus a growing subset of SystemVerilog, and its README describes it as a compiler that generates code for back-end tools such as its simulation runtime. Verilator (LGPL-3.0 or Artistic-2.0) accepts Verilog and SystemVerilog, including UVM, performs lint checks and compiles the design into multithreaded C++ or SystemC, which is why its README calls it the fastest Verilog/SystemVerilog simulator. GHDL (GPL-2.0) is for VHDL: an analyzer, compiler, simulator and experimental synthesizer with full support for the 1987, 1993 and 2002 versions of the standard and partial support for 2008 and 2019, running on Linux, Windows and macOS. Here is how they differ, and where a visual logic simulator like digiwleea fits alongside them.
Which one to use
Pick by language and goal. For VHDL, GHDL is the open-source choice, and it can write GHW, VCD or FST waveforms for a viewer such as GTKWave. For Verilog with ordinary testbenches (initial blocks, delays, $display), Icarus Verilog is the classic, easy starting point in many courses. For large SystemVerilog designs where speed matters, such as whole processors, Verilator's compiled C++ models are the fastest of the three, at the cost of writing the testbench around the generated model. All three are free and run from the command line; if you would rather not install anything, our EDA Playground comparison covers running HDL in the browser. (digiwleea is an independent project, not affiliated with any of these projects.)
Where digiwleea fits
These tools simulate code. digiwleea simulates circuits you draw: you build gates from CMOS transistors in the browser, then adders, multiplexers, flip-flops, registers, memory and a small 8-bit CPU, watching every wire's value, with every part checked against its truth table. It complements an HDL course rather than replacing an HDL simulator: see what the always block or process you wrote becomes in gates, then export your circuit to Verilog or VHDL. It does not run HDL code itself; it imports a combinational subset of VHDL. Choosing a language? See Verilog vs VHDL.
| Icarus Verilog, Verilator and GHDL | digiwleea | |
|---|---|---|
| Input | Verilog, SystemVerilog or VHDL source code | Circuits you draw, from transistors up |
| Output | Simulation results and waveform files | Live wire values in the browser, truth tables, timelines |
| Install | Command-line tools for your OS | Nothing: it runs in the browser |
| HDL | Simulates it | Exports circuits to Verilog and VHDL; free lessons on both |
| Price | Free and open source | Free lab and Act I; Premium for the full course |
The three side by side
| Icarus Verilog | Verilator | GHDL | |
|---|---|---|---|
| Language | Verilog (IEEE 1364), part of SystemVerilog | Verilog and SystemVerilog, including UVM | VHDL 1987, 1993, 2002; partial 2008, 2019 |
| How it simulates | Compiles to code for its runtime | Compiles to multithreaded C++ or SystemC | Compiles with LLVM, GCC or a built-in generator |
| Extras | Classic event-driven testbenches | Lint checks; JSON output for tools | GHW, VCD and FST waveforms; experimental synthesis |
| License | GPL-2.0 | LGPL-3.0 or Artistic-2.0 | GPL-2.0 |
Learning the languages? digiwleea's free lessons start with Verilog, sequential Verilog, VHDL and VHDL processes, and HDLBits has practice problems with a built-in checker.
No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.
More comparisons: HDL, FPGA and chip design tools
See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.
Open the digiwleea lab →Frequently asked
What is the difference between Icarus Verilog and Verilator?
Icarus Verilog compiles Verilog for its own event-driven runtime and handles classic testbenches with delays directly. Verilator compiles Verilog or SystemVerilog into C++ or SystemC models, which run much faster but are driven from a C++ testbench or a supported flow. Icarus is the easier start; Verilator suits large, speed-critical designs.
Is GHDL for Verilog or VHDL?
VHDL. GHDL fully supports the 1987, 1993 and 2002 versions of the VHDL standard and partially supports 2008 and 2019. For Verilog, use Icarus Verilog or Verilator.
Are Icarus Verilog, Verilator and GHDL free?
Yes. All three are open source: Icarus Verilog and GHDL under GPL-2.0, Verilator under LGPL-3.0 or the Artistic License 2.0.
Is there a visual alternative to HDL simulators for learning?
Yes. A schematic logic simulator such as digiwleea lets you build and watch the circuits directly in the browser, from transistors to a CPU, and export them to Verilog or VHDL once you understand them.