Full adder using 8-to-1 multiplexers, live
A full adder can be built from two 8-to-1 multiplexers and nothing else. A, B and Cin drive the three select lines of both muxes, and each mux's eight data inputs are the output's truth-table column as constants: the sum mux gets 0, 1, 1, 0, 1, 0, 0, 1 and the carry mux 0, 0, 0, 1, 0, 1, 1, 1.
An 8-to-1 multiplexer with n = 3 select lines can produce any function of three variables: the selects pick one of the eight rows of the truth table, and the data input wired to that row holds the answer. This is the plainest way to implement a truth table in hardware, the same idea as a lookup table in an FPGA or a small ROM. It needs no simplification, at the price of a larger mux than the full adder using two 4-to-1 muxes, which moves Cin from the selects to the data inputs. The 8-to-1 mux here is the verified 8-to-1 multiplexer, saved as a part. The full adder using a decoder is the same truth-table idea with a decoder and OR gates.
Open this circuit in the lab →
What you need
- 2× 8-to-1 MUX: one for S and one for Cout, with S2 = A, S1 = B, S0 = Cin
- 2× constant: 0 (GND) and 1 (VDD) on the data inputs
Step by step
- Place inputs
A,BandCin, two 8-to-1 muxes and probesSandCout. - Wire A, B and Cin to S2, S1 and S0 on both muxes.
- Sum mux: D0 to D7 = 0, 1, 1, 0, 1, 0, 0, 1 (the minterms 1, 2, 4 and 7 are 1).
- Carry mux: D0 to D7 = 0, 0, 0, 1, 0, 1, 1, 1 (minterms 3, 5, 6 and 7).
- Try all eight rows: each mux outputs the data input of the selected row.
Full adder truth table: the mux data inputs
| A | B | Cin | Row (data input) | S | Cout |
|---|---|---|---|---|---|
| 0 | 0 | 0 | D0 | 0 | 0 |
| 0 | 0 | 1 | D1 | 1 | 0 |
| 0 | 1 | 0 | D2 | 1 | 0 |
| 0 | 1 | 1 | D3 | 0 | 1 |
| 1 | 0 | 0 | D4 | 1 | 0 |
| 1 | 0 | 1 | D5 | 0 | 1 |
| 1 | 1 | 0 | D6 | 0 | 1 |
| 1 | 1 | 1 | D7 | 1 | 1 |
The S and Cout columns, read top to bottom, are the constants on D0 to D7 of each mux. All eight rows are checked on the live circuit before the page is built.
You can also read the full theory in the lesson on the multiplexer as a universal block. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Arithmetic
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the full adder using 8:1 multiplexers in the lab →Frequently asked
How do you implement a full adder using an 8:1 multiplexer?
Put A, B and Cin on the three select lines and wire each data input to the output value for that row: 0, 1, 1, 0, 1, 0, 0, 1 for the sum and 0, 0, 0, 1, 0, 1, 1, 1 for the carry. One 8:1 mux per output.
Can an 8:1 mux implement any 3-variable function?
Yes. With the three variables on the selects, the eight data inputs are simply the function's truth table, so any of the 256 possible functions fits.
Why use 4:1 muxes instead of 8:1 for a full adder?
A 4:1 mux is smaller. Putting only A and B on the selects and feeding Cin, NOT Cin, 0 or 1 as data gives the same full adder with two 4:1 muxes and a NOT gate.