8-to-1 multiplexer using 4-to-1 multiplexers, live
An 8-to-1 multiplexer can be built from two 4-to-1 multiplexers and one 2-to-1 multiplexer. S1 and S0 drive both 4-to-1 muxes, so one picks from D0 to D3 and the other from D4 to D7; S2 then drives the 2-to-1 mux that chooses which half reaches the output Y.
Splitting the select bits is the whole idea. The low bits S1 S0 choose a position within a group of four, and the high bit S2 chooses the group: with S2 S1 S0 = 101, both 4-to-1 muxes select their input 1 (D1 and D5), and S2 = 1 passes the upper one, D5. The same split works for any size: a 16-to-1 mux from five 4-to-1 muxes uses S1 S0 inside the groups and S3 S2 to pick one of four groups, and a 32-to-1 mux can be made from four 8-to-1 muxes and one 4-to-1 mux. Some textbook answers use a third 4-to-1 mux instead of the 2-to-1, with S2 on S0 and S1 tied to 0; that works too but wastes half the mux. Each MUX block here is a verified part: the 4-to-1 multiplexer and the 2-to-1 multiplexer from logic gates; open the circuit in the lab to look inside. The same 8-to-1 mux can also be a tree of seven 2-to-1 muxes, or one gate-level 8-to-1 multiplexer.
Open this circuit in the lab →
What you need
- 2× 4-to-1 MUX: S1 S0 select: D0 to D3 in one, D4 to D7 in the other
- 1× 2-to-1 MUX: S2 select: the lower half (0) or the upper half (1), output Y
Step by step
- Place data inputs
D0toD7, selectsS2,S1,S0and a probeY. - Wire D0 to D3 into the first 4-to-1 mux and D4 to D7 into the second, and connect S1 and S0 to the selects of both.
- Feed the first mux's output to input 0 of a 2-to-1 mux and the second's to input 1, with S2 as its select.
- The 2-to-1 mux output is
Y. - Set S2 S1 S0 to any number from 0 to 7 and toggle that data input: Y follows it, and no other input changes Y.
8-to-1 mux from 4-to-1 muxes: truth table
| S2 | S1 | S0 | First 4:1 mux | Second 4:1 mux | Y |
|---|---|---|---|---|---|
| 0 | 0 | 0 | D0 | D4 | D0 |
| 0 | 0 | 1 | D1 | D5 | D1 |
| 0 | 1 | 0 | D2 | D6 | D2 |
| 0 | 1 | 1 | D3 | D7 | D3 |
| 1 | 0 | 0 | D0 | D4 | D4 |
| 1 | 0 | 1 | D1 | D5 | D5 |
| 1 | 1 | 0 | D2 | D6 | D6 |
| 1 | 1 | 1 | D3 | D7 | D7 |
Before the page is built, all eight select values are checked on the live circuit with 18 data patterns each (all 0, all 1, and every single 1 and single 0), which shows the selected input reaches Y and no other input leaks through. One size up: the 16-to-1 mux using 8-to-1 muxes.
You can also read the full theory in the lesson on multiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Selecting, routing and decoding
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 8-to-1 multiplexer from 4-to-1 muxes in the lab →Frequently asked
How do you design an 8 to 1 mux using 4 to 1 muxes?
Use two 4-to-1 muxes with S1 and S0 on both, one for D0 to D3 and one for D4 to D7, and a 2-to-1 mux with S2 as its select to choose between their outputs.
How many 4 to 1 muxes are needed for an 8 to 1 mux?
Two, plus a 2-to-1 mux to pick between them. If only 4-to-1 muxes are available, a third one can do that job with S2 on its S0 input and S1 tied to 0.
How many 4:1 multiplexers are needed for a 16:1 multiplexer?
Five: four that each pick one of four inputs with S1 S0, and a fifth that picks one of those four outputs with S3 S2.
How do you make a 32 to 1 mux from 8 to 1 muxes?
Use four 8-to-1 muxes on S2 S1 S0, one per group of eight inputs, and a 4-to-1 mux on S4 S3 to choose the group.
Why build a large multiplexer from smaller ones?
Standard chips and library cells come in small sizes, such as the 74HC153 dual 4-to-1 and the 74HC151 8-to-1, and a tree of small muxes reuses one tested block instead of drawing a wide gate-level circuit.