16-to-1 multiplexer using 8-to-1 multiplexers, live
A 16-to-1 multiplexer can be built from two 8-to-1 multiplexers and one 2-to-1 multiplexer. S2, S1 and S0 drive both 8-to-1 muxes, so one picks from D0 to D7 and the other from D8 to D15; S3 then drives the 2-to-1 mux that chooses which half reaches the output Y.
The select bits split into a position and a group. The low three bits S2 S1 S0 choose one of eight inputs inside each half, and the top bit S3 chooses the half: with S3 S2 S1 S0 = 1011, both 8-to-1 muxes select their input 3 (D3 and D11), and S3 = 1 passes the upper one, D11. If only 8-to-1 muxes are available, a third one can stand in for the 2-to-1, with S3 on its S0 and S2 S1 tied to 0, at the cost of six unused inputs. The same idea scales: a 32-to-1 mux is four 8-to-1 muxes and a 4-to-1 mux on S4 S3. Each 8-to-1 block here is the verified 8-to-1 multiplexer from logic gates, and the last stage is the 2-to-1 multiplexer, all saved as parts; open the circuit in the lab to look inside. Compare the other ways to build the same mux: 16-to-1 from five 4-to-1 muxes, and one size down, the 8-to-1 mux from 4-to-1 muxes.
Open this circuit in the lab →
What you need
- 2× 8-to-1 MUX: S2 S1 S0 select: D0 to D7 in one, D8 to D15 in the other
- 1× 2-to-1 MUX: S3 select: the lower half (0) or the upper half (1), output Y
Step by step
- Place data inputs
D0toD15, selectsS3toS0and a probeY. - Wire D0 to D7 into the first 8-to-1 mux and D8 to D15 into the second, and connect S2, S1 and S0 to the selects of both.
- Feed the first mux's output to input 0 of a 2-to-1 mux and the second's to input 1, with S3 as its select.
- The 2-to-1 mux output is
Y. - Set S3 S2 S1 S0 to any number from 0 to 15 and toggle that data input: Y follows it, and no other input changes Y.
16-to-1 mux from 8-to-1 muxes: truth table
| S3 | S2 S1 S0 | First 8:1 mux | Second 8:1 mux | Y |
|---|---|---|---|---|
| 0 | 000 | D0 | D8 | D0 |
| 0 | 001 | D1 | D9 | D1 |
| 0 | 010 | D2 | D10 | D2 |
| 0 | 011 | D3 | D11 | D3 |
| 0 | 100 | D4 | D12 | D4 |
| 0 | 101 | D5 | D13 | D5 |
| 0 | 110 | D6 | D14 | D6 |
| 0 | 111 | D7 | D15 | D7 |
| 1 | 000 | D0 | D8 | D8 |
| 1 | 001 | D1 | D9 | D9 |
| 1 | 010 | D2 | D10 | D10 |
| 1 | 011 | D3 | D11 | D11 |
| 1 | 100 | D4 | D12 | D12 |
| 1 | 101 | D5 | D13 | D13 |
| 1 | 110 | D6 | D14 | D14 |
| 1 | 111 | D7 | D15 | D15 |
Before the page is built, all 16 select values are checked on the live circuit with 34 data patterns each (all 0, all 1, and every single 1 and single 0), which shows the selected input reaches Y and no other input leaks through. Twice as many inputs: the 32-to-1 mux using 8-to-1 muxes.
You can also read the full theory in the lesson on multiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Selecting, routing and decoding
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 16-to-1 multiplexer from 8-to-1 muxes in the lab →Frequently asked
How do you design a 16 to 1 mux using 8 to 1 muxes?
Use two 8-to-1 muxes with S2 S1 S0 on both, one for D0 to D7 and one for D8 to D15, and a 2-to-1 mux with S3 as its select to choose between their outputs.
How many 8 to 1 muxes are needed for a 16 to 1 mux?
Two, plus a 2-to-1 mux to choose between them. With 8-to-1 muxes only, a third one can do that job with S3 on its lowest select input and the other selects tied to 0.
How do you make a 32 to 1 mux using 8 to 1 muxes?
Four 8-to-1 muxes on S2 S1 S0, one per group of eight inputs, and a 4-to-1 mux on S4 S3 to choose the group.
How many 4 to 1 muxes make a 16 to 1 mux?
Five: four that each pick one of four inputs with S1 S0, and a fifth that picks one of those four outputs with S3 S2.
How many select lines does a 16 to 1 multiplexer have?
Four, because 2^4 = 16: S3 S2 S1 S0 together give the number of the input that reaches Y.