Mod-9 counter: count 0 to 8 and wrap, live
A mod-9 counter counts 0 to 8 and then returns to 0, nine states, using four flip-flops. This one is a 4-bit synchronous counter whose next state is forced to 0000 when the count reaches 8 (1000), and 8 is detected by Q3 alone.
Three flip-flops give only eight states, so nine states need four, and seven of the sixteen codes go unused. The counter itself is the usual 4-bit synchronous one: D0 = NOT Q0, and each higher bit toggles when every lower bit is 1. To stop at 8, notice that in the sequence 0 to 8 the only state with Q3 = 1 is 8 itself, so the reset signal is simply CLR OR Q3, and when it is 1 every D input is forced to 0. That makes mod-9 one of the cheapest counters to decode, cheaper than the decade counter, which needs Q3 AND Q0 to find 9. The same count-and-clear pattern gives the mod-7 and mod-12 counters. The live circuit opens with CLR on; switch it to 0 and the running clock counts 0 to 8 and wraps.
Open this circuit in the lab →
What you need
- 4× D flip-flop: Q3 to Q0, on one clock
- 3× XOR: toggle logic for Q1, Q2 and Q3
- 2× AND: the carry chain Q1 Q0 and Q2 Q1 Q0
- 1× OR: reset = CLR OR Q3
- 2× NOT: NOT Q0 and NOT reset
- 4× AND: each D gated by NOT reset
Step by step
- Place a clock
CLK, an inputCLR, four D flip-flops and probesQ3toQ0. - Build a 4-bit synchronous counter: D0 = NOT Q0, D1 = Q1 XOR Q0, D2 = Q2 XOR Q1 Q0, D3 = Q3 XOR Q2 Q1 Q0.
- Make the reset:
CLR OR Q3, then invert it. - AND each next-state signal with the inverted reset before it reaches its D input, so the clock after 8 loads 0000.
- Turn CLR off and watch the count run 0 to 8 and wrap.
Mod-9 count sequence
| Count | Q3 Q2 Q1 Q0 | Next |
|---|---|---|
| 0 | 0000 | 1 |
| 1 | 0001 | 2 |
| 2 | 0010 | 3 |
| 3 | 0011 | 4 |
| 4 | 0100 | 5 |
| 5 | 0101 | 6 |
| 6 | 0110 | 7 |
| 7 | 0111 | 8 |
| 8 | 1000 | 0 |
Before the page is built, a 22-clock run (a clear, the count once round and back, a clear mid-run) is checked on all four outputs after every clock. Q3 is high for one clock in nine, so it is also a divide-by-9 output, though not a square wave.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the Mod-9 counter in the lab →Frequently asked
How many flip-flops are needed for a mod 9 counter?
Four. Three flip-flops give only 2^3 = 8 states, one short of nine, so a fourth is needed and seven of the sixteen states go unused.
How do you design a mod 9 counter?
Take a 4-bit counter and clear it after 8. Synchronously, detect 8 and force the next state to 0000; because 8 is the only state from 0 to 8 with Q3 set, Q3 alone detects it. An asynchronous ripple design instead detects 9 (Q3 AND Q0) and clears at once.
Can a mod 9 counter divide a clock by 9?
Yes. Any output that repeats once every nine clocks, such as Q3 here, has one ninth of the clock frequency, but its duty cycle is 1/9 rather than 50%.