Mod-6 synchronous counter using JK flip-flops, live
A mod-6 synchronous counter counts 000, 001, 010, 011, 100, 101 and back to 000, six states on three JK flip-flops that share one clock. Designed with the JK excitation table, its inputs are J0 = K0 = 1, J1 = Q0 Q2', K1 = Q0, J2 = Q1 Q0 and K2 = Q0.
Three flip-flops can count to 8, so a mod-6 counter must skip two states, 110 and 111. The design follows the textbook procedure. Write the state table: each present state and the next one. For every flip-flop, look up the J and K that produce its change in the JK excitation table (0 to 0 needs J = 0, 0 to 1 needs J = 1, 1 to 0 needs K = 1, 1 to 1 needs K = 0, the other input being a don't-care X). Then simplify each J and K with a K-map, treating the unused states 110 and 111 as don't-cares too. The flip-flops here are the master-slave JK flip-flops from NAND gates, saved as parts, so the count changes when the clock falls, and CLR clears all three. The counter is self-starting: if it ever lands in 110 it goes to 111 and then 000. The same design with the full 8 states is the 3-bit synchronous counter using JK flip-flops, and a mod-6 counter built from D flip-flops is the mod-6 counter.
Open this circuit in the lab →
What you need
- 3× JK flip-flop: master-slave, falling edge, with clear; Q2 Q1 Q0 is the count
- 1× AND: J1 = Q0 AND Q2'
- 1× AND: J2 = Q1 AND Q0
- 1× constant 1: J0 = K0 = 1, so Q0 toggles on every clock
Step by step
- Place a clock
CLK, an inputCLR, three JK flip-flops on the same clock and probesQ2,Q1,Q0. - Flip-flop 0: tie J0 and K0 to 1, so Q0 toggles every clock.
- Flip-flop 1: J1 = Q0 AND Q2', K1 = Q0.
- Flip-flop 2: J2 = Q1 AND Q0, K2 = Q0.
- Turn CLR off and watch Q2 Q1 Q0 count 000 to 101, then wrap to 000.
State table and JK excitation
| Q2 Q1 Q0 | Next | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 101 | X | 0 | 0 | X | 1 | X |
| 101 | 000 | X | 1 | 0 | X | X | 1 |
X is a don't-care. With 110 and 111 also don't-cares, the K-maps give J2 = Q1 Q0, K2 = Q0, J1 = Q0 Q2', K1 = Q0 and J0 = K0 = 1. Before the page is built, the live circuit runs 20 clocks, two full counts with a clear in between, and Q2, Q1 and Q0 are checked after every edge.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the mod-6 synchronous counter using JK flip-flops in the lab →Frequently asked
How do you design a mod-6 synchronous counter using JK flip-flops?
Use three JK flip-flops on one clock. Write the state table for 000 to 101, find each J and K from the JK excitation table, mark 110 and 111 as don't-cares, and simplify with K-maps: J0 = K0 = 1, J1 = Q0 Q2', K1 = Q0, J2 = Q1 Q0, K2 = Q0.
How many flip-flops does a mod-6 counter need?
Three, because two flip-flops count only to 4 and three count to 8. A mod-6 counter uses six of the eight states.
Is this mod-6 counter self-starting?
Yes. From the unused state 110 it goes to 111 and then to 000, so it rejoins the count within two clocks.
What is the difference between a synchronous and an asynchronous mod-6 counter?
In a synchronous counter every flip-flop shares the clock and the next state comes from logic, as here. An asynchronous (ripple) mod-6 counter chains the clocks and resets itself when it reaches 110, which briefly shows that state.
What is the JK excitation table?
It lists the J and K needed for each change of Q: 0 to 0 needs J = 0, K = X; 0 to 1 needs J = 1, K = X; 1 to 0 needs J = X, K = 1; 1 to 1 needs J = X, K = 0.