2-bit up/down counter: synchronous circuit, live

A 2-bit up/down counter counts 0, 1, 2, 3 when UP = 1 and 3, 2, 1, 0 when UP = 0, with both flip-flops on one clock. Bit 0 toggles on every clock, and bit 1 toggles when Q0 = 1 counting up or Q0 = 0 counting down: D0 = NOT Q0, D1 = Q1 XOR (Q0 XNOR UP).

Counting up, a bit flips when all lower bits are 1; counting down, when they are all 0. With only one lower bit, that condition is Q0 when UP = 1 and NOT Q0 when UP = 0, which is exactly Q0 XNOR UP. A D flip-flop that should toggle gets its own output XORed with the toggle condition, so D1 = Q1 XOR (Q0 XNOR UP). As T or JK flip-flops the design reads T0 = 1 and T1 = Q0 UP + Q0' UP'. Because both flip-flops share the clock, the direction can change at any time and the next clock simply counts the other way. Each D is ANDed with NOT CLR, a synchronous clear to 00. The same idea scales bit by bit to the 4-bit up/down counter; the up-only version is the mod-4 counter, and the ripple up/down counter does it without a shared clock.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

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To cite it: digiwleea, “2-bit up/down counter”, https://digiwleea.wleeaf.dev/tools/build/up-down-counter-2bit/

What you need

2× D flip-flop: Q1 and Q0, on one clock
1× NOT: D0 = NOT Q0
1× XNOR: the toggle condition of bit 1: Q0 XNOR UP
1× XOR: D1 = Q1 XOR (Q0 XNOR UP)
2× AND: synchronous clear: each D ANDed with NOT CLR

Step by step

Place two D flip-flops on one clock, inputs UP and CLR, and probes Q1 and Q0.
D0 = NOT Q0, so bit 0 toggles on every clock.
XNOR Q0 with UP, then XOR that with Q1 for D1.
AND both D inputs with NOT CLR, clear once, then clock with UP = 1: 00, 01, 10, 11, 00.
Set UP = 0 and keep clocking: the count runs 11, 10, 01, 00, 11.

2-bit up/down counter state table

UP	Q1 Q0 now	Q0 XNOR UP	Q1 Q0 next
1	00	0	01
1	01	1	10
1	10	0	11
1	11	1	00
0	00	1	11
0	11	0	10
0	10	1	01
0	01	0	00

Before the page is built, the live circuit runs 16 clocks: up for six, down for six and up again, with both outputs checked after every clock.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Registers and counters

3-bit synchronous down counter 3-bit synchronous up/down counter using JK flip-flops 3-bit synchronous counter (JK)4-bit up/down counter 4-bit synchronous counter decade counter 4-bit asynchronous up/down counter 7-segment display counter 4-bit ripple down counter mod-6 counter 4-bit ripple counter mod-6 synchronous counter using JK flip-flops

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 2-bit up/down counter in the lab →

Frequently asked

How do you design a 2-bit up/down counter?

Bit 0 toggles every clock (D0 = Q0'). Bit 1 toggles when Q0 = 1 counting up and when Q0 = 0 counting down, so its toggle condition is Q0 XNOR UP and D1 = Q1 XOR (Q0 XNOR UP).

How many flip-flops does a 2-bit up/down counter need?

Two, one per bit. The direction input changes only the logic in front of the second flip-flop.

What are the T flip-flop inputs of a 2-bit up/down counter?

T0 = 1 and T1 = Q0 UP + Q0' UP', which is Q0 XNOR UP.