Asynchronous (ripple) up/down counter, 4-bit, live
An asynchronous up/down counter is a ripple counter whose stages are clocked by Q' to count up or by Q to count down. One XOR per stage does the choosing: stage k + 1 is clocked by Q_k XOR UP, which is Q_k' when UP = 1 and Q_k when UP = 0.
In a ripple counter only the first flip-flop sees the clock; each later stage toggles when the stage before it changes in the right direction. Taking the clock from Q' makes a stage toggle when the one below falls from 1 to 0 (a carry, counting up), and taking it from Q makes it toggle when the one below rises from 0 to 1 (a borrow, counting down), as in the ripple counter and the ripple down counter. An XOR with UP picks between the two without a multiplexer. There is a catch, and it is why textbooks warn about this design: changing UP flips every inner clock line at once, and a flipped line can look like a clock edge, which toggles that stage and corrupts the count. So change direction only while CLR holds the counter at 0 (as the check below does), or use a synchronous design such as the 4-bit up/down counter or the 2-bit up/down counter, where the direction can change at any time. CLR is asynchronous.
Open this circuit in the lab →
What you need
- 4× D flip-flop with clear: one per bit, D tied to its own Q' so it toggles on every edge it sees
- 3× XOR: the clock of stages 1 to 3: Q of the stage below XOR UP
Step by step
- Place four D flip-flops with clear, inputs
UPandCLR, a clock and probesQ0toQ3. - Tie each flip-flop's Q' to its own D, so each one toggles.
- Clock stage 0 from CLK, and each later stage from the XOR of the previous stage's Q with UP.
- Hold CLR on, set UP = 1, release CLR and clock: 0, 1, 2 and up past 15 to 0.
- Turn CLR on, set UP = 0, release CLR and clock: 15, 14, 13 and on down.
Which output clocks the next stage
| UP | Next stage clocked by | It toggles when the stage below | Counts |
|---|---|---|---|
| 1 | Q' (Q XOR 1) | falls from 1 to 0 | up |
| 0 | Q (Q XOR 0) | rises from 0 to 1 | down |
Before the page is built, the live circuit runs 40 clocks: up from a clear past the 15 to 0 wrap, then a clear while UP changes, then down past the 0 to 15 wrap, with all four outputs checked after every clock.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 4-bit asynchronous up/down counter in the lab →Frequently asked
How does an asynchronous up/down counter work?
It is a ripple counter in which each stage is clocked by Q' of the stage below to count up or by Q to count down. An XOR of Q with the UP input, or a 2-to-1 mux, selects which one.
What is the problem with an asynchronous up/down counter?
Changing the direction input flips the inner clock lines, which can clock some stages and corrupt the count. The ripple delays also make the outputs pass through wrong values while they settle.
What is the difference between a synchronous and an asynchronous up/down counter?
In a synchronous counter every flip-flop shares the clock and logic decides which bits toggle, so all outputs change together and the direction can change at any time. In an asynchronous one each stage clocks the next.