3-bit synchronous up/down counter using JK flip-flops, live
A 3-bit synchronous up/down counter counts 0 to 7 and back, with a direction input UP. Three JK flip-flops share one clock and work as T flip-flops (J = K = T): T0 = 1, T1 = Q0 XNOR UP and T2 = (Q0 XNOR UP)(Q1 XNOR UP).
Counting up, a bit toggles when every bit below it is 1 (011 + 1 = 100); counting down, it toggles when every bit below it is 0 (100 - 1 = 011). One expression covers both: Q_j XNOR UP is 1 when Q_j is 1 and UP = 1, or when Q_j is 0 and UP = 0, so the toggle input of each stage is the AND of Q_j XNOR UP over the lower bits. The textbook form T1 = UP Q0 + UP' Q0' is the same thing written as a sum of products. The flip-flops are the master-slave JK flip-flops from NAND gates, saved as parts, with J and K tied together so each acts as a T flip-flop; the count changes when the clock falls, and CLR clears all three. The 4-bit version built from D flip-flops is the 4-bit up/down counter, the up-only JK design is the 3-bit synchronous counter, and the ripple version is the asynchronous up/down counter.
Open this circuit in the lab →
What you need
- 3× JK flip-flop: master-slave, falling edge, with clear; J = K = T for each stage
- 2× XNOR: Q0 XNOR UP and Q1 XNOR UP
- 1× AND: T2 = (Q0 XNOR UP) AND (Q1 XNOR UP)
- 1× constant 1: T0 = 1: Q0 toggles every clock
Step by step
- Place a clock
CLK, inputsUPandCLR, three JK flip-flops on the same clock and probesQ2,Q1,Q0. - Flip-flop 0: J0 = K0 = 1.
- Flip-flop 1: J1 = K1 = Q0 XNOR UP.
- Flip-flop 2: J2 = K2 = (Q0 XNOR UP) AND (Q1 XNOR UP).
- Turn CLR off: with UP = 1 the count goes 000, 001, ... 111, 000; set UP = 0 and it counts down, 111 after 000.
Toggle inputs for each direction
| UP | T0 | T1 | T2 | Count |
|---|---|---|---|---|
| 1 | 1 | Q0 | Q1 Q0 | up: 0, 1, 2, ... 7, 0 |
| 0 | 1 | Q0' | Q1' Q0' | down: 7, 6, 5, ... 0, 7 |
Before the page is built, the live circuit runs 24 clocks: a clear, nine counts up (through the 7 to 0 wrap), nine down (through the 0 to 7 wrap) and up again, with Q2, Q1 and Q0 checked after every edge.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 3-bit synchronous up/down counter using JK flip-flops in the lab →Frequently asked
How do you design a 3-bit synchronous up/down counter using JK flip-flops?
Use three JK flip-flops on one clock with J = K = T. Set T0 = 1, T1 = UP Q0 + UP' Q0' (Q0 XNOR UP) and T2 = UP Q1 Q0 + UP' Q1' Q0'. UP = 1 counts up and UP = 0 counts down.
Why does a down counter toggle a bit when the lower bits are 0?
Subtracting 1 borrows through every 0 bit at the bottom and stops at the first 1, so a bit changes exactly when all the bits below it are 0, the mirror of counting up.
How many flip-flops does a 3-bit up/down counter need?
Three, one per bit. The direction input only changes the toggle logic between them.
What is the difference between a synchronous and an asynchronous up/down counter?
In a synchronous counter all flip-flops share the clock and the toggle logic decides which bits change, so they change together. In an asynchronous (ripple) counter each flip-flop is clocked by the one before, through a mux that picks Q or Q' for the direction.