Down counter: 3-bit synchronous circuit, count 7 to 0, live
A 3-bit synchronous down counter counts 7, 6, 5 down to 0 and wraps back to 7, with all three flip-flops on one clock. A bit toggles when every bit below it is 0, so with D flip-flops D0 = NOT Q0, D1 = Q1 XNOR Q0 and D2 = Q2 XOR NOR(Q1, Q0).
Counting down is counting up with the bits inverted. Going up, a bit flips when all the bits below it are 1 (the carry); going down, it flips when all the bits below it are 0 (the borrow). So the toggle condition for Q1 is NOT Q0, which a D flip-flop gets as D1 = Q1 XOR NOT Q0, the same as Q1 XNOR Q0, and for Q2 it is NOT Q1 AND NOT Q0, which is NOR(Q1, Q0). With T or JK flip-flops the same design reads T0 = 1, T1 = Q0' and T2 = Q1' Q0'. All flip-flops share the clock, so every output changes on the same edge, unlike the ripple down counter. Each D is ANDed with NOT CLR for a synchronous clear to 000; the first clock after that gives 111. Compare the 3-bit synchronous up counter, and the 4-bit up/down counter, which picks either direction with one input.
Open this circuit in the lab →
What you need
- 3× D flip-flop: Q2, Q1 and Q0, on one clock
- 1× NOT: D0 = NOT Q0
- 1× XNOR: D1 = Q1 XNOR Q0
- 1× NOR: Q1' Q0', the borrow into bit 2
- 1× XOR: D2 = Q2 XOR NOR(Q1, Q0)
- 3× AND: synchronous clear: each D ANDed with NOT CLR
Step by step
- Place three D flip-flops on one clock, with probes
Q2,Q1,Q0. - D0 = NOT Q0: the low bit toggles on every clock.
- D1 = Q1 XNOR Q0: bit 1 toggles when Q0 is 0.
- D2 = Q2 XOR NOR(Q1, Q0): bit 2 toggles when Q1 and Q0 are both 0.
- AND each D with NOT CLR, clear once, then clock: 000, 111, 110, 101, 100, 011, 010, 001, 000.
3-bit down counter state table
| Q2 Q1 Q0 now | Q2 Q1 Q0 next | Bits that toggle |
|---|---|---|
| 000 (0) | 111 (7) | all three |
| 111 (7) | 110 (6) | Q0 |
| 110 (6) | 101 (5) | Q0, Q1 |
| 101 (5) | 100 (4) | Q0 |
| 100 (4) | 011 (3) | all three |
| 011 (3) | 010 (2) | Q0 |
| 010 (2) | 001 (1) | Q0, Q1 |
| 001 (1) | 000 (0) | Q0 |
Before the page is built, the live circuit runs 20 clocks (two full countdowns, with a clear in the middle), and all three outputs are checked after every clock.
You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 3-bit synchronous down counter in the lab →Frequently asked
How do you design a 3-bit synchronous down counter?
Each bit toggles when all lower bits are 0. With T flip-flops T0 = 1, T1 = Q0' and T2 = Q1' Q0'; with D flip-flops D0 = Q0', D1 = Q1 XNOR Q0 and D2 = Q2 XOR (Q1' Q0').
What is the difference between an up counter and a down counter?
An up counter toggles a bit when all lower bits are 1; a down counter toggles it when all lower bits are 0. Reading an up counter's inverted outputs also gives a down count.
What comes after 000 in a 3-bit down counter?
111. The count wraps from 0 to 7, the way a subtraction borrows past zero.
How many flip-flops does a 3-bit down counter need?
Three, one per bit; three bits give the eight states 0 to 7.