4-bit ripple (asynchronous) down counter, live
A ripple down counter is a ripple counter that counts 15, 14, 13 down to 0: four toggling flip-flops where each stage is clocked by the true output Q of the stage before it, instead of Q'. Only the first flip-flop sees the real clock.
Every flip-flop here is a D flip-flop with Q' fed back to D, so it toggles on each rising edge of its own clock. In the ripple up counter, stage k + 1 is clocked by Q' of stage k, so it toggles when stage k falls from 1 to 0, which is a carry. Clock it from Q instead and it toggles when stage k rises from 0 to 1, which happens exactly when counting down needs a borrow: 0000 goes to 1111, then 1110, and so on. The design costs nothing extra, only a different wire per stage, and it has the ripple counter's drawbacks too: each stage waits for the one before it, so for a moment during a change the outputs show other values before they settle. That is why counters inside a CPU are usually synchronous, like the 3-bit synchronous down counter. CLR is asynchronous, clearing all four stages at once.
Open this circuit in the lab →
What you need
- 4× D flip-flop with clear: one per bit, D tied to its own Q' so it toggles on every edge it sees
Step by step
- Place four D flip-flops with clear, probes
Q0toQ3, a clock andCLR. - Tie each flip-flop's Q' back to its own D, so each one toggles.
- Clock the first stage from CLK, and each later stage from the Q (not Q') of the stage before it.
- Turn CLR on and off: the count is 0000.
- Clock it: 1111 (15), 1110, 1101 and on down to 0000, then 1111 again.
Ripple down counter: first steps after a clear
| Clock | Q3 Q2 Q1 Q0 | Value |
|---|---|---|
| cleared | 0000 | 0 |
| 1 | 1111 | 15 |
| 2 | 1110 | 14 |
| 3 | 1101 | 13 |
| 4 | 1100 | 12 |
| 5 | 1011 | 11 |
| 15 | 0001 | 1 |
| 16 | 0000 | 0 |
Before the page is built, the live circuit runs 24 clocks, through the 0 to 15 wrap and a second clear, with all four outputs checked after every clock.
You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
More builds: Registers and counters
All 246 build guides, by topic
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 4-bit ripple down counter in the lab →Frequently asked
How do you make a ripple counter count down?
Clock each stage from the Q output of the previous stage instead of Q' (with rising-edge flip-flops). Each stage then toggles when the one before it goes from 0 to 1, which is the borrow of a down count.
What is an asynchronous down counter?
A down counter whose flip-flops do not share a clock: only the first gets the clock, and each later stage is clocked by the stage before it. It is the down-counting version of the ripple counter.
What is the disadvantage of a ripple down counter?
The delays add up along the chain, so the outputs change one after another and briefly show wrong values. A synchronous counter changes all bits on the same edge.